Digital Controlled Inverter for Uninterruptible Power Supplies with Infineon Tricore TC1775 32bit processor
by Nicola Bergamin (see contacts info)

Introduction

From the System Engineer standpoint, the design of midrange or high size UPS appliances faces two different control needs: on one hand, there is a request for fast and highly specialized Digital Signal Processing capability, due to intrinsic high bandwith of the power conversion control loop; equally important, there is also the need for sophisticated supervisory architecture aimed at real-time supervision of the whole process, data communication and interfacing.

UPS control requirements

DSP technology well suits high speed digital control contraints encountered in a UPS design, while other characteristics, such as available on-chip memory, peripheral set and logic instruction set are generally weak. Moreover, DSPs often have a specific BUS design that pushes for speed. This intrinsically contrasts the request of linear space addressing. In DSPs interrupts are somehow limited both in number and in complexity.

RISC CPUs (both traditional 16 and 32bits) give good system management and communication capability, but, comparing at equal clock speed, are typically 3 to 5 times slower than an equivalent class DSP in number-crunching tasks such as: closed loop digital controllers, IIR filters, array and matrix multiply.

The established trade-off for these two specific and nearly contrasting needs is the usage of a specific intelligent unit for each task:

• a fast specialized DSP for Inverter real time control,
• a general pourpose CPU for system level supervision.

Full UPS control by TC1775 TriCore

New approaches are available as technology advances and the cost of high-end CPUs decreases. Recently introduced Infineon TriCore 32-bit RISC CPU core gathers the best of both embedded architectures: powerful DSP capability, and extended RISC 32bit CPU, offering in a single chip the optimal solution for average to high complexity UPS appliances. Moreover, fast event handling is performed directly by the PCP (Peripheral Control Processor).

• superscalar pipeline allows for up to three instruction per single machine cycle-two Macs per cycle,
• specific DSP instruction set,
• harvard bus geometry for program and data,
• 40MHz clock.

• 1KB code prediction cache,
• strong bit handling capability (compiler support),
• fast register bank switching for immediate context switching: optimal compiler support,
• 32 level interrupt mechanism, 256 possible sources,
• 16Meg addressing space.

• PCP (Peripheral Control Processor) for fast communication between CPU and peripherals.
  Peripherals act as an autonomous processor, thus avoiding overhead of main CPU core,
• Twin CAN BUS 2.0B,
• 5us A/D converter, 2sync channels, programmable 8/10/12bits,
• GPTA: Powerful centered PWM generation unit.

UPS System Development

The system development approach for TriCore based UPS design slightly changes compared to other architectures: a single set of tools, debuggers and hardware platform is used by different developers at different design scopes. We do not want to be too rigid in task subdivision, but just for reference, let's evaluate the following:

Communication, Interface, Diagnostics

This is the higher system layer (hence, software layer), and involves mainly the CPU-RISC core. C-programming with the support of a Real Time OS is recommended, even if the RTOS is not strictly necessary. The underlying inner machine complexity is hidden to this stage. Typical applications consist in serial communication , display and touch screen mimic panel, CAN Bus or Profibus communication.
Perhaps, one may claim that fast bus communication is a part of control startegy itself. OK, right: for example, CAN bus may be used as a real time control link for current sharing strategy in paralleled UPSs.

Process Supervision

This part is strictly linked to the Power Control task (below), and acts as a master logic of the whole machine, and paricularly for power control stages. It is mainly peformed by the CPU RISC core; for example: phase locked loop, alarms, measurement handling, threshold conditioning are all handled by this system layer.

Power Control

Low level current control and switch firing pattern control involves mainld DSP core and makes strong usage of peripheral intelligent management. It can be use both C-programming and assembly programming for killer (!) control tasks: PFC, reversible inverter matrix, active filter, boost control and output inverter control are all tasks that require control granularity and sampling time accuracy in the field of 10us or less. This of course requires skipping the usual RTOS constraints, and, by the way, often obliges to write "dirty" assembly routines.

Tools

Tricore is equipped by on-board OCDS (On Chip Debug Support) plus JTAG interface. This debugging concept is similar to what implemented in Motorola 68xxx 32 bit CPU, or in ARM7 cores.
On-board OCDS allows accurate debugging with unexpensive external hardware (parallel port of a PC , no more). More expensive emulators (Ashling and others, see links) allow also trace and more sophisticated damn tricky features.

WARNING: Of course,..of course,.. the developer certainly is aware of the risk incurring when, in a live power environment while debugging, the CPU core gets stopped amidst a PWM waveform generation cycle.
At an early stage of development,it is recommended that safe inverter algorithm debugging is made on a low-voltage inverter model, with proper backup overcurrent mechanisms.

References

TriCore Technology and Development Support

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