In this page we give a concise representation of the evaluation board we used to achieve what has been previously explained:

Figure 2:         Block scheme of the ADDS-2181 EZ-LITE.

Note that in the connection between AD1847 and the DSP it's the first that plays the role of the master. Then we report the main features of the 2181 and the Stereo Sound Port Codec:

ADSP-2181
Performance   25 Instruction Cycle Time from 20Mhz Crystal @ 5.0 Volts
                            40 MIPS Sustained Performance
                            Single-Cycle Instruction Execution
                            Single-Cycle Contest Switch
                            3-Bus Architacture Allows Dual Operand Fetches in Every
                                Instruction Cycle
                            Multifunction Instruction
                            Power-Down Mode Featuring Low CMOS Standby
                                Power Dissipation with 100 Cycle Recovery from Power-Down
                                Condition
                            Low Power Dissipation in Idle Mode

Integration       ADSP-2100 Family Code Compatible, with Instruction Set
                                Extension
                            80K Bites of On-Chip RAM, Configured as
                                16K Words On-Chip Program Memory RAM
                                16K Words On-Chip Data Memory RAM
                            Dual Purpose Program Memory for Both Instruction and Data
                                Storage
                            Independent ALU, Multiplier/Accumulator and Barrel Shifter
                                Computational Units
                            Two Independent Data Address Generators
                                   Powerful Program Sequencer Provides Zero Overhead Looping and
                            Programmable 16-bit Internal Timer with Prescaler

System Interface
                             16-bit Internal DMA Port for High Speed Access to On-Chip
                                 Memory
                             Programmable Wait State Generation
                            Two Double-Buffered Serial Ports with Companding Hardware and
                                 Automatic Data Buffering
                            Six External Interrupts
                            13 Programmable Flag Pins Provide Flexible System Sygnaling
                            ICE-Port™ Emulator Interface Supports Debugging in Final
                                Systems

AD-1847 STEREO SOUND PORT CODEC
                            Single-Chip Integrated SD Digital Audio Stereo Codec
                            Supports the Microsoft Windows Sound System
                            Multiple Channels of Stereo Input
                            Analog and Digital Signal Mixing
                            Programmable Gain and Attenuation
                            On-Chip Signal Filters
                                Digital Interpolation and Decimation
                                Analog Output Low-Pass
                            Sample Rates from 5.5 kHz to 48 kHz
                            Serial Digital Interface Compatible with ADSP-21xx Fixed Point
                                DSP

To learn more about ADI's DSP, please visit Analog Devices DSP homepage.

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